The present invention relates to a semiconductor integrated circuit having the function of switching between an operation mode and a standby mode. More specifically, the present invention relates to a technique which reduces a leak current without erasing data stored in a logic circuit when a semiconductor integrated circuit is in a standby mode.
There has recently been increasingly growing demand for low power consumption with respect to a semiconductor device. As one factor that will increase power consumption of the semiconductor device, there is known a leak current that flows through each of MOS transistors and diodes which constitute an integrated circuit. The leak current is of a current that flows when each MOS transistor or the like is in an off state or a reverse bias state. In order to suppress the power consumption, the leak current of the integrated circuit is preferably reduced.
As one technique for reducing the leak current, there has been known an MTCMOS (Multi Threshold-Complementary Metal Oxide Semiconductor) technique (refer to, for example, the paragraph 0003 and FIG. 8 in a patent document 1 (Japanese Unexamined Patent Publication No. Hei 8(1996)-321763)). In an MTCMOS integrated circuit of the patent document 1, a logic circuit is constituted of low threshold MOS transistors. Such a logic circuit is connected to a pseudo source line VDDV. Further, the pseudo source line VDDV is connected to a source line VDD via a high threshold MOS transistor Qs. When the logic circuit is in an operation mode, the MOS transistor Qs is turned on to supply power from the source line VDD to the logic circuit. When the logic circuit is in a standby mode, the MOS transistor Qs is turned off to avoid the supply of a source potential to the logic circuit. A MTCMOS integrated circuit (refer to, for example, the paragraph 0003 and FIG. 18 of a patent document 2 (Japanese Unexamined Patent Publication No. Hei 11(1999)-214962)) of the patent document 2 is nearly similar to above.
The MOS transistor is reduced in leak current as its operating threshold value becomes higher but, on the other hand, reduced in operating speed. Thus, in the integrated circuit of the patent document 1, the logic circuit is constituted of the low threshold MOS transistors, and the high threshold MOS transistor is used as a power switch, thereby making a high-speed operation and a leak-current reduction compatible.
As another technique for reducing a leak current, there has been known a VTCMOS (Variable Threshold-Complementary Metal Oxide Semiconductor) technique (refer to, for example, the paragraphs 0030 and 0031 of the patent document 2). In the VTCMOS technique, the potential of a substrate formed with an integrated circuit is reduced in an operation mode and made high in a standby mode or an IDDQ testing (Quiescent Current Testing: test for detecting a variation in process from the value of a quiescent current). Thus, an operating threshold value of each MOS transistor is lowered in the operation mode and made high in the standby mode or the like. Accordingly, the MOS transistor is operated at high speed in the operation mode and small in leak current in the standby mode or the like. A phenomenon that the operating threshold value rises when the substrate potential is set higher than a source potential, is referred to as a substrate bias effect.
However, the conventional MTCMOS technique is accompanied by a drawback that when the power switch (i.e., high threshold MOS transistor which performs connection/disconnection between the pseudo source line and the source line VDD) is turned off and thereby brought to the standby mode, data retained in the logic circuit is erased. If a specific circuit for data storage is added, it is also then possible to prevent disappearance of the retained data in the standby mode. In this case, however, a new drawback occurs in that a circuit scale increases.
The conventional VTCMOS technique is accompanied by drawbacks that since the operating threshold values of all MOS transistors formed in the same substrate are simultaneously changed, the parasitic capacity becomes large and the time required to perform switching between the operation mode and the standby mode becomes longer.